Method of manufacturing a semiconductor device with non-volatile memory comprising a memory cell with an access gate and with a control gate and a charge storage region

ABSTRACT

Method of manufacturing a semiconductor device comprising a semiconductor body ( 1 ) which is provided at a surface ( 2 ) with a non-volatile memory comprising a memory cell with a gate structure ( 4 ) with an access gate ( 19 ) and a gate structure ( 3 ) with a control gate ( 5 ) and a charge storage region situated between the control gate ( 5 ) and the semiconductor body ( 1 ), such as a floating gate ( 6 ). In this method on the surface ( 2 ) of the semiconductor body ( 1 ) a first one of said gate structures is formed with side walls ( 10 ) extending substantially perpendicular to the surface, a conductive layer is deposited ( 13 ) on and next to said first gate-structure, the conductive layer is subjected to a planarizing treatment until the first gate structure is exposed and the so planarized conductive layer is patterned so as to form at least a part of the other gate structure adjoining the first gate structure. Said patterning of the planarized conductive layer is performed in that the planarized conductive layer ( 14 ) is etched back so as to expose an upper portion ( 15 ) of the side walls of the first gate structure, a spacer ( 18 ) is formed on the exposed upper portion ( 15 ) of the side walls of first gate structure and the conductive layer ( 16 ) is etched anisotropically using the spacer as a mask. Thus very small memory cells can be realized.

The invention relates to a method of manufacturing a semiconductordevice comprising a semiconductor body which is provided at a surfacewith a non-volatile memory comprising a memory cell with a gatestructure with an access gate and a gate structure with a control gateand a charge storage region situated between the control gate and thesemiconductor body, in which method on the surface of the semiconductorbody a first one of said gate structures is formed with side wallsextending substantially perpendicular to the surface, a conductive layeris deposited on and next to said first gate-structure, the conductivelayer is subjected to a planarizing treatment until the first gatestructure is exposed and the so planarized conductive layer is patternedso as to form at least a part of the other gate structure adjoining thefirst gate structure.

In practice the charge storage region can be a floating gate or a gatedielectric comprising a distribution of mutually separated trappingcenters. Such a gate dielectric may, for example, be a silicon oxidelayer with contaminations, for example metal particles, distributedtherein, the contaminations thereby providing the trapping centers.However, a more widespread way is the use of a gate dielectriccomprising a double layer of two different materials, which form aborder layer supplying the mutually separated trapping centers. Usingthe above mentioned method both gate structures adjoin each other, sothat small sized memory cells can be made. In practice a non-volatilememory of course will comprise a very large number of these memorycells.

From WO 01/67517 A1 a method as mentioned before is known, in whichmethod the planarized conductive layer is patterned by anisotropicetching, after a photo resist mask has been formed on the first gatestructure and next to the first gate structure on the planarizedconductive layer.

The use of the photo resist mask in the known method will lead to extracosts, but what is more important that it will influence the size of thememory cell. The photo resist mask can not be placed exactly in adesired position, but overlay errors, if any, should be considered. Thiswill lead to a relatively large photo resist mask and thus to arelatively large memory cell.

The invention has for its object to provide a method, which offers thepossibility of manufacturing very small memory cells with relativelysmall costs.

According to the invention the method mentioned in the opening paragraphis therefore characterized in that to perform the patterning of theplanarized conductive layer, the planarized conductive layer is etchedback so as to expose an upper portion of the side walls of the firstgate structure, a spacer is formed on the exposed upper portion of theside walls of first gate structure and the conductive layer is etchedanisotropically using the spacer as a mask.

The spacer on the exposed upper portions of the side walls of the firstone of the gate structures can be made at minimum costs, without using aphoto resist mask, in a self aligned manner. Such spacers on verticalwalls are formed in practice by depositing an auxiliary layer and thenetching said auxiliary layer anisotropically until only spacers are lefton the vertical walls. The width of the spacers then equals about thethickness of the auxiliary layer. Because the spacer thus can be madewith a very small width and because overlay errors have not to beconsidered, very small memory cells can be realized.

A first preferred embodiment of the method according to the invention ischaracterized in that as the first one of said gate structures the gatestructure with the control gate and the charge storage region situatedbetween the control gate and the semiconductor body is formed, afterwhich the side walls of this gate structure are covered by an insulatinglayer and the surface of the semiconductor body next to the gatestructure with a gate dielectric, the conductive layer is deposited,planarized, etched back and patterned using the spacer formed on theexposed portions of the gate structure as a mask so as to form the gatestructure with the access gate. As said before the charge storage regioncan be a floating gate or a gate dielectric comprising a distribution ofmutually separated trapping centers. This gate structure with controlgate and charge storage region can be etched anisotropically in a stackof layers formed on the surface of the semiconductor body. Thenautomatically said side walls perpendicular to the surface of thesemiconductor are formed. These side walls can be covered easily by aninsulating layer by depositing a layer followed by an anisotropic etchuntil the top of the gate structure is exposed or also by an oxidationtreatment, when, what is usual in practice, the gates in the gatestructure are formed in layers of polycrystalline silicon. On top of thestack of said layers an extra layer may be deposited which may act as aprotection layer during forming the insulating layer on the side wallsand also as a stop layer during the planarizing treatment.

A second preferred embodiment of the method according to the inventionis characterized in that as the first one of said gate structures thegate structure with the access gate is formed, after which the sidewalls of this gate structure are covered by an insulating layer, theconductive layer is deposited, planarized, etched back and patternedusing the spacer formed on the exposed portions of the gate structure asa mask so as to form the control gate of the gate structure with thecontrol gate and the charge storage region situated between the controlgate and the semiconductor body. This embodiment of the method offers,as will be demonstrated later with reference to the drawing, theopportunity of realizing a lot of gate structures with control gate andcharge storage region, without using photo resist masks.

These and other aspects of the invention will be apparent from and beelucidated with reference to the embodiments described hereinafter andshown in the drawing. In the drawing:

FIGS. 1 to 9 show a diagrammatic cross-sectional views of successivestages in the manufacture of a non volatile memory cell using a firstembodiment of the method according to the invention,

FIGS. 10 to 15 show a diagrammatic cross-sectional views of successivestages in the manufacture of a non volatile memory cell using a secondembodiment of the method according to the invention,

FIGS. 16 to 21 show a diagrammatic cross-sectional views of successivestages in the manufacture of a non volatile memory cell using a thirdembodiment of the method according to the invention,

FIGS. 22 to 30 show a diagrammatic cross-sectional views of successivestages in the manufacture of a non volatile memory cell using a forthembodiment of the method according to the invention and

FIGS. 31 to 36 show a diagrammatic cross-sectional views of successivestages in the manufacture of a non volatile memory cell using a fifthembodiment of the method according to the invention.

FIGS. 1 to 9 show in diagrammatic cross-sectional views successivestages of manufacturing a semiconductor device with a non-volatilememory comprising a memory cell with a gate structure 4 with an accessgate 19 and a gate structure 3 with a control gate 5 and a chargestorage region 6 situated between the control gate 5 and a semiconductorbody 1. For the sake of clarity the manufacture of only one of suchcells is described, but it will be clear, that in practice a nonvolatile memory comprises a lot of these memory cells.

As shown in FIG. 1 on a surface 2 of the semiconductor body 1, here ap-type doped silicon body, a first one of the gate structures, in thisexample the gate structure 3 with the control gate 5 and the chargestorage region situated between the control gate and the semiconductorbody are formed. In this example the charge storage region is a floatinggate 6. The gate structure 3 here comprises a tunnel dielectric 7, afloating gate 6, an inter gate dielectric 8 and a top layer 9. The gatestructure is formed by an anisotropic etch of a stack of layers. Thetunnel dielectric 7 may be formed in a 7 nm thick layer of siliconoxide, the floating gate 6 in an about 200 nm thick layer ofpolycrystalline silicon, the inter gate dielectric 8 in an about 18 nmthick layer of ONO (a 6 nm thick layer of silicon oxide, a 6 nm thicklayer of silicon nitride and a 6 nm thick layer of silicon oxide), thecontrol gate 5 in an about 200 nm thick layer of polycrystalline siliconand the top layer 9 in an about 100 nm thick layer of silicon nitride.Because the gate structure 3 is formed by an anisotropic etch thestructure has side walls 10 extending substantially perpendicular to thesurface 2 of the semiconductor body 1.

As shown in FIG. 2 the side walls 10 are covered by an about 30 nm thickinsulating layer 11, here a layer of silicon oxide and the surface nextto the gate structure 3 is covered with a gate dielectric 12, here anabout 10 nm thick layer of silicon oxide. The insulating layer 11 may beformed by thermal oxidation of the gate structure or by depositing alayer followed by an anisotropic etch which is stopped as soon as thetop layer 9 is exposed.

After the gate structure 3 is formed and its side walls are covered withthe insulating layer 11, a relatively thick conductive layer 13, here anabout 500 nm thick layer of polycrystalline silicon is deposited on andnext to said first gate-structure 3. As shown in FIG. 3 the conductivelayer 13 then is subjected to a planarizing treatment until the toplayer 9 of the first gate structure 3 is exposed. The so planarizedconductive layer 14 then is patterned so as to form at least a part ofthe other gate structure adjoining the first gate structure 3.

The patterning of the planarized conductive layer 14 is performed asshown in the FIGS. 4, 5 and 6. In a first step, as shown in FIG. 4 theplanarized conductive layer 14 is etched back so as to expose an upperportion 15 of the side walls 10 of the first gate structure 3. Thisetching back can be carried out by means of an isotropic etch oranisotropic etch or as a combination of an isotropic etch and ananisotropic etch. From the conductive layer 14 then remains a part 16.Then a spacer 18 is formed on the exposed upper portion 15 of the sidewalls 10 of first gate structure 3. The spacers 18 are formed in a usualmanner by depositing a layer 17 here a layer of silicon oxide, followedby an anisotropic etch until the top layer 9 of the first gate structure3 is exposed. As shown in FIG. 6, then the remaining part of theconductive layer 16 is etched anisotropically using the spacer as amask. Thus the second gate structure 4 is formed her consisting of agate dielectric 12 and an access gate 19.

Then as shown in the FIG. 7 in a usual manner lightly doped source- anddrain zones 20 are formed by ion implantation. Then as shown in FIG. 8further spacers 21 are formed and highly doped source- and drain zones22 are formed. As shown in FIG. 9 the source- and drain zones the may beprovided with a top layer 23 of a silicide.

The spacer 18 on the exposed upper portions 15 of the side walls 15 ofthe first one of the gate structures 3 can be made at minimum costs,without using a photo resist mask, in a self aligned manner. Because thespacer 18 can be made with a very small width and because overlay errorshave not to be considered, very small memory cells can be realized.

In the FIGS. 1 to 9 a first embodiment of the method is shown wherebythe first one of said gate structures 3 is the gate structure with thecontrol gate 8 and the charge storage region 6 between the control gateand the semiconductor body is formed after which the side walls of thisgate structure 3 are covered by an insulating layer 11, the surface ofthe semiconductor body next to the gate structure with a gate dielectric12, the conductive layer 13 is deposited, planarized, etched back andpatterned using the spacer 18 whereby the gate structure 4 with theaccess gate 19 is formed. The gate structure 3 can be formed easily in astack of layers whereby the top layer 9 may act as a protection layerduring forming the insulating layer 11 on the side walls and also as astop layer during the planarizing treatment.

In the examples that follow, as far as possible, for corresponding partsof the memory cells the same reference numbers are used as in themanufacture of the memory cell described before.

FIGS. 10 to 15 show in diagrammatic cross-sectional views successivestages of manufacturing a semiconductor device with a non-volatilememory comprising a memory cell as in the preceding example with a gatestructure 4 with an access gate 19 and a gate structure 3 with a controlgate 5 and a charge storage region 6 situated between the control gateand the semiconductor body.

As shown in FIG. 10 the charge storage region here is formed by a stack24 of insulating layers provided with trapping centers, here an about 6nm thick layer of silicon oxide formed on an about 6 nm thick layer ofsilicon nitride formed on an about 6 nm thick layer of tunnel oxideformed on the surface 2 of the semiconductor body. On this stack thecontrol gate 5 and the top layer 9 are formed. The side walls 10 areprovided with the insulating layer 11 and the surface next to thegate-structure 3 with the layer gate oxide.

Then, as shown in FIG. 11, the conductive layer is deposited, planarizedand etched back of which layer the remaining part 16 is shown. Thespacer 18 here is formed in a different way as described before. First arelatively thin auxiliary insulating layer 25 is deposited, here anabout 10 nm thick layer of silicon oxide, and then a further layer 17 inthis example a layer of polycrystalline silicon, the same material asthe conductive layer 16. Then the layer 17 is etched anisotropicallyuntil the layer 25 on top of the gate structure 3 is exposed and thelayer 25 is etched anisotropically until the top layer 9 is exposed.When as shown in FIG. 13 the remaining part 16 of the conductive layeris etched the spacer 18 is also removed. When the remaining part of theinsulating layer 25 is removed the structure as shown in FIG. 13 isobtained.

When as shown in FIG. 14 the spacer 21 is formed also a spacer 26 isformed, but a part 27 of the access gate 19 remains exposed. When thesilicide regions 23 are formed on the source- and drain regions of thememory cells in the same process step silicide regions 28 are formed onthe access gate 19. Said gate thus gets a relatively low electricalresistance.

FIGS. 16 to 21 show in diagrammatic cross-sectional views successivestages of manufacturing a memory cell with a gate structure 4 with anaccess gate 19 and a gate structure 3 with a control gate 5 and a chargestorage region 6 situated between the control gate and the semiconductorbody using a third embodiment of the method according to the invention.In this example as the first one of said gate structures the gatestructure 4 with the access gate 19 is formed. Here the about 400 nmthick access gate 19 of polycrystalline silicon is formed on an about 10nm thick layer of gate oxide 12 and covered by the top layer 9 ofsilicon nitride.

As shown in FIG. 17, the gate structure 4 is provided wit an about 30 nmthick insulating layer 11 on its side walls 10, here by thermaloxidation. At the same time, in the same process step, next to thisstructure 4 an about 6 nm thick silicon oxide layer 29 is formed. Somesteps later, as shown in FIG. 18, the conductive layer 13 is deposited.This layer 13 is, as shown in FIG. 19, planarized whereby the top layer9 on the gate structure 4 is exposed. The planarized layer 14, is etchedback and patterned using the spacer 18 formed on the exposed portions 15of the gate structure 4 as a mask so as to form the control gate 5 ofthe gate structure 4 with the control gate 5 and the charge storageregion 30 situated between the control gate 5 and the semiconductor body1.

This method gives the opportunity of realizing a lot of gate structures4 with control gate 5 and charge storage region between that controlgate and the semiconductor body, without using photo resist masks.

In this example the charge storage region between the control gate 5 andthe semiconductor body 1 is formed by a layer 30 consisting of a siliconnitride which is deposited on the gate structure 4 before the conductivelayer 13 is deposited and the silicon oxide layer 29. After the controlgate 5 has been is formed, as shown in FIG. 20, the lightly dopedsource- and drain zones are formed, the spacer 21 is formed. Then, asshown in FIG. 21, the layer 30 as well as the layer of silicon oxide 29formed on the surface 2 of the semiconductor body 1 are etched using thespacer 21 as a mask, the highly doped source- and drain zones 22 andsilicide regions are formed. Using the described method this memory cellcan be made easily.

In the next two preferred embodiments of the manufacturing of memorycells, as shown in FIGS. 22 to 23, the gate structure 4 with the accessgate 19 on gate oxide 12 is formed, the side walls 10 of this gatestructure 4 are covered with an insulating layer 11 and thesemiconductor body 1 next to the gate structure 4 with tunnel dielectriclayer 7. Then a floating gate on the tunnel dielectric 4 and coveredwith an inter gate dielectric will be formed next to the gate structure4, this floating gate having a top surface lower than the gate structure4 with the access gate 19. Then the conductive layer 13 is deposited,planarized, etched back and patterned using the spacer 18 formed on theexposed portions 25 of the gate structure 4 with the access gate 19 as amask so as to form the control gate 5 on the inter gate dielectric 8.This method offers the opportunity of realizing a number of simplememory cells.

The first example is described with reference to FIGS. 24 to 30. Asshown in FIG. 24 the gate structure 4 is covered with a further layer 31of conductive material, here an about 600 nm thick layer ofpolycrystalline silicon. As shown in FIG. 13 this further conductivelayer 31 is planarized until top layer 9 is exposed. Because the furtherlayer has a thickness larger than that of the gate structure 4 theplanarized further conductive layer 32 has a flat surface 34. Then, asshown in FIG. 26 the planarized further conductive layer 33 is etchedback until portions 35 of the gate structure 4 are exposed. This etchingback can be carried out by means of an isotropic etch or anisotropicetch or as a combination of an isotropic etch and an anisotropic etch.The remaining part 36 of the further conductive layer has a thickness ofabout 100 nm.

The structure as shown in FIG. 26 the is covered with a layer 37 of aninter gate dielectric her a layer composed made up of a 6 nm thick layerof silicon oxide, a 6 nm thick layer of silicon nitride and a 6 nm thicklayer of silicon oxide. Then, as shown in FIG. 28, the conductive layeris deposited, planarized so as to form the planarized conductive layer14. The planarized layer 14 then is etched back to form the conductivelayer 16. The layer 16 then is patterned using the spacer 18 formed onthe exposed portions 15 of the gate structure 4 as a mask so as to formthe control gate 5 in the etched back conductive layer 16 as well as thefloating gate 6 in the further etched back conductive layer 36.

After the control gate 5 has been is formed, the lightly doped source-and drain zones 20 are formed. Then the spacer 21 is formed and, asshown in FIG. 30, the highly doped source- and drain zones 22 andsilicide regions 23 are formed.

As can be seen in the FIG. 30 the inter gate dielectric 37 is presentbetween the access gate 19 and the control gate 5 so that the electriccoupling between these gates is relatively small.

The second example is described with reference to FIGS. 31 to 36. In thememory cell made using this method the electric coupling between thecontrol gate 5 and access gate 19 as also small and further the floatinggate 6 is fully surrounded by the control gate 5 so that the electriccoupling between the control gate 5 and the floating gate 6 isrelatively large.

This manufacture of the second example starts with the structure asshown in FIG. 25, where next to the gate structure 4 comprising theaccess gate 19 the about 100 nm thick further conductive layer 36 hadbeen formed. Then, as shown in FIG. 31, a further spacer 38 is formedand the conductive layer 36 is etched so as to form the floating gate 6on the tunnel dielectric layer 7 next to the gate structure 4 with theaccess gate. After removal of the further spacer 38, the so formedfloating gate 6 is provided with a layer of an inter gate dielectric 37,the conductive layer is deposited, planarized, whereby the conductivelayer 14 is formed. The layer 14 then is etched back to form conductivelayer 16. After this the spacer 18 is formed and the conductive layer 14is patterned using the spacer 14 as a mask so as to form the controlgate 5 on the floating gate 6.

After the control gate 5 has been is formed, the lightly doped source-and drain zones 20 are formed. Then the spacer 21 is formed and, asshown in FIG. 30, the highly doped source- and drain zones 22 andsilicide regions 23 are formed.

The further spacer 38 has a width smaller than the width of the spacer18 so that the floating gate 6 is fully surrounded by the control gate5. The electrical coupling between both gates then is optimal. Such asmall spacer could also be made by depositing a conductive layerfollowed by an anisotropic etch whereby a small conductive spacer wouldbe left next to the gate structure 4. The method described beforehowever is more reliable.

It will be clear that the spacer 18 as shown in FIG. 13 after patterningthe conductive layer 14 may be removed from the upper portions of thesecond one of the gate structures. These upper portions form the accessgate 19 in FIGS. 9 and 15 or the control gate 5 in the FIGS. 21, 30 and36. The gates thus exposed after patterning the conductive layer 16 thencan be provided with a silicide top layer as shown in FIG. 15. The sameof course is applicable for the top layer 9 formed on the first one ofthe gate structures.

Preferably the spacer 18 then is formed as shown in FIGS. 11 and 12 in arelatively thin first 25 and a relatively thick second layer 17. Duringan anisotropic etch both layers are etched until the top of the firstone of the gate structures is exposed. The first and second layers arechosen in such a way that the second relatively thick layer can beetched selectively with respect to the relatively thin first layer. Whenthe second relatively thick layer 17 is a layer of the same material asthe material of the conductive layer 13 the relatively thick part of thespacer 18 is removed in the same etching process in which the conductivelayer 14 is patterned. The thin layer part 25 under the spacer 18 thenis used as the mask.

1. Method of manufacturing a semiconductor device comprising asemiconductor body which is provided at a surface with a non-volatilememory comprising a memory cell with a gate structure with an accessgate and a gate structure with a control gate and a charge storageregion situated between the control gate and the semiconductor body, inwhich method on the surface of the semiconductor body a first one ofsaid gate structures is formed with side walls extending substantiallyperpendicular to the surface, a conductive layer is deposited on andnext to said first gate-structure, the conductive layer is subjected toa planarizing treatment until the first gate structure is exposed andthe so planarized conductive layer is patterned so as to form at least apart of the other gate structure adjoining the first gate structure,characterized in that, to perform said patterning of the planarizedconductive layer, the planarized conductive layer is etched back so asto expose an upper portion of the side walls of the first gatestructure, a spacer is formed on the exposed upper portion of the sidewalls of first gate structure and the conductive layer is etchedanisotropically using the spacer as a mask.
 2. Method as claimed inclaim 1, characterized in that, as the first one of said gate structuresthe gate structure with the control gate and the charge storage regionsituated between the control gate and the semiconductor body is formed,after which the side walls of this gate structure are covered by aninsulating layer and the surface of the semiconductor body next to thegate structure with a gate dielectric, the conductive layer isdeposited, planarized, etched back and patterned using the spacer formedon the exposed portions of the gate structure as a mask so as to formthe gate structure with the access gate.
 3. Method as claimed in claim1, characterized in that, as the first one of said gate structures thegate structure with the access gate is formed, after which the sidewalls of this gate structure are covered by an insulating layer, theconductive layer is deposited, planarized, etched back and patternedusing the spacer formed on the exposed portions of the gate structure asa mask so as to form the control gate of the gate structure with thecontrol gate and the charge storage region situated between the controlgate and the semiconductror body.
 4. Method as claimed in claim 3,characterized in that, after the gate structure with the access gate isformed and the side walls of this gate structure are covered with aninsulating layer, a charge storage region is formed next to the gatestructure in the form of a collection of mutually separated trappingcenters, after which the conductive layer is deposited, planarized,etched back and patterned using the spacer formed on the exposedportions of the gate structure with the access gate as a mask so as toform the control gate on the charge storage region.
 5. Method as claimedin claim 3, characterized in that, after the gate structure with theaccess gate is formed and the side walls of this gate structure arecovered with an insulating layer, a floating gate on a tunnel dielectricand covered with an inter gate dielectric is formed next to the gatestructure, this floating gate having a top surface lower than the gatestructure with the access gate, after which the conductive layer isdeposited, planarized, etched back and patterned using the spacer formedon the exposed portions of the gate structure with the access gate as amask so as to form the control gate on the inter gate dielectric. 6.Method as claimed in claim 5, characterized in that, for forming thefloating gate on the tunnel dielectric next to the gate structure withthe access gate, a further layer of conductive material is deposited,planarized, etched back to expose upper portions of side walls of thegate structure with the access gate and covered with a layer of an intergate dielectric, the conductive layer is deposited, planarized, etchedback and patterned using the spacer formed on the exposed portions ofthe gate structure with the access gate as a mask so as to form thecontrol gate in the conductive layer as well as the floating gate in thefurther conductive layer.
 7. Method as claimed in claim 5, characterizedin that, for forming the floating gate on the tunnel dielectric next tothe gate structure with the access gate, a further layer of conductivematerial is deposited, planarized, etched back to expose upper portionsof side walls of the gate structure with the access gate, after which afurther spacer is formed on the exposed upper portions and the furtherconductive layer is etched using the further spacer as a mask, afterwhich the further spacer is removed and the so formed floating gate isprovided with a layer of an inter gate dielectric, the conductive layeris deposited, planarized, etched back and patterned using the spacerformed on the exposed portions of the gate structure with the accessgate as a mask so as to form the control gate on the floating gate. 8.Method as claimed, in claim 1 characterized in that, before thedeposition of the conductive layer on top of the first one of said gatestructures an insulating layer is formed which may act as a stop layerduring the planarization of he conductive layer.
 9. Method as claimed,in claim 1, characterized in that, after patterning the conductive layerthe spacer on the upper portions of the second one of the gatestructures is removed.
 10. Method as claimed in claim 9, characterizedin that for forming the spacer a relatively thin first and a relativelythick second layer are deposited, after which an anisotropic etch isperformed whereby both layer are etched until the top of the first oneof the gate structures is exposed, whereby the first and second layerare chosen, so the second relatively thick layer can be etchedselectively with respect to the relatively thin first layer.
 11. Methodas claimed in claim 10, characterized in that the second relativelythick layer is a layer of the same material as the material of theconductive layer.